Damian Thong

Damian Thong of Macquarie Capital asked about the strategic partnerships with Technoprobe and FormFactor. He questioned whether the push into die/wafer level testing would be additive to the TAM or lead to efficiencies that reduce it, and if this move could create an industry standard, placing Advantest ahead of competitors.

Answer

Executive Douglas Lefever explained that increasing complexity necessitates more test insertions at the wafer level and that the partnerships are designed to create a 'total solution' for customers. He described the partnerships as neither accretive nor dilutive to TAM but essential for addressing complexity. Regarding competition, he emphasized the goal is customer benefit and driving integration, and that more such partnerships are expected.

Damian Thong asked about the strategic partnerships with Technoprobe and FormFactor, questioning if the push into die/wafer level testing would be additive to the TAM and what the long-term implications are for growth and competitive positioning.

Answer

Executive Douglas Lefever explained the partnerships are crucial for creating a 'total solution' test cell to address rising complexity, requiring deep technical collaboration. He sees more test insertions at the wafer sort stage rather than efficiency gains that would shrink the market. Lefever emphasized the goal is to drive integration for customer benefit, which helps the company maintain a strong position, rather than being simply accretive or dilutive.

Asked about the development timeline for next-generation HBM test solutions (HBM4), the company's market position with ASIC companies and large tech firms developing in-house silicon, and whether this ASIC-related business would be a material growth driver.

Answer

The company confirmed they are already actively developing solutions for HBM4, working closely with customers for a release within the next two years. They stated they have a 'very, very strong position' with the key ASIC companies and hyperscalers developing their own silicon. This business is already a material contributor to revenue and is expected to be a meaningful part of the SoC market going forward.

Damian Thong from Macquarie Capital Securities asked for an update on the development timeline for next-generation HBM test solutions like HBM4. He also inquired about Advantest's progress in securing business from large tech companies developing their own in-house silicon.

Answer

Executive Douglas Lefever confirmed that development for HBM4 solutions is already active and proceeding in lockstep with customers for release within the next two years. He stated that Advantest holds a 'very, very strong position' with the key ASIC companies that work with hyperscalers and that this business is already a material and meaningful part of the SoC market.

Damian Thong of Macquarie Capital asked about the strategic partnerships with Technoprobe and FormFactor, questioning if the push into die/wafer level testing will be additive to the TAM or lead to efficiencies that reduce it, and how this positions Advantest competitively.

Answer

Executive Douglas Lefever explained that the partnerships are driven by the need to address rising complexity by creating a total test cell solution. He sees more test insertions at the wafer/die level, not fewer. Lefever clarified the goal is not about being 'accretive' but about partnering to deliver integrated solutions for customers' benefit, which strengthens their competitive position by addressing complex technical challenges collaboratively.

Asked for the business outlook for the system-level test (SLT) business for the next fiscal year and whether the HPC market for SLT could eventually grow to the size of the mobility market.

Answer

The SLT business is expected to be 'relatively flat' next year, as its traditional mobility market remains soft. However, there is growing demand for SLT in HPC, AI, and ADAS. The company believes the HPC market for SLT can eventually grow to the size of the mobility market, but it will take time, driven by the need for automation as volumes increase.

Requested more details on cryogenic etching technology, including its application to different NAND layers and sales timing. Also asked about wafer bonding adoption among DRAM manufacturers.

Answer

Cryogenic etching evaluation is currently focused on 400+ layers, with sales recognition expected to begin in calendar year 2025. It will become more important as NAND investment doubles in 2025. For wafer bonding, the company confirmed inquiries have doubled but declined to provide specific customer or sales figures.