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    Takeru Hanaya

    Senior Equity Analyst at SMBC Nikko Securities

    Takeru Hanaya is a Senior Equity Analyst at SMBC Nikko Securities, specializing in the coverage of leading Japanese industrial and technology manufacturers such as Advantest Corp, TOELY, TOPPAN Holdings, SCREEN Holdings, Tokyo Electron, and KOKUSAI Electric. He is recognized for his thorough research and has participated in multiple company earnings calls, demonstrating active engagement with management teams and offering detailed analysis on sector performance. Hanaya has been consistently affiliated with SMBC Nikko Securities as a named coverage analyst for several years, with no public records of prior firms, indicating a stable and focused career trajectory within the Japanese equity research space. While specific performance metrics and rankings are not publicly available, his ongoing coverage of top-listed firms underscores his professional credibility and influence, although professional credentials such as FINRA registrations or securities licenses are not disclosed in available sources.

    Takeru Hanaya's questions to TOELY leadership

    Takeru Hanaya's questions to TOELY leadership • Q3 2025

    Question

    Questioned the rationale behind the forecast for NAND investment to double in CY2025, given that vendors are cutting production volumes, and asked about the outlook for 2026.

    Answer

    The forecasted doubling of NAND investment is for brownfield technology migration, not new greenfield capacity. Customers are investing to migrate to newer nodes to reduce their unit costs and improve profitability. For 2026, the company tentatively assumes the current investment level will continue, with cutting-edge NAND customers expected to increase investment.

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    Takeru Hanaya's questions to TOELY leadership • Q4 2024

    Question

    Questioned the company's strategy for partnerships in the hybrid bonding space, particularly for HBM, and asked for the expected timeline for hybrid bonding for NAND and backside PDN to become significant.

    Answer

    The executive explained that the company sees opportunities in die-to-wafer bonding and is exploring possibilities within its supply chain rather than doing everything in-house. The timeline for adoption is: NAND flash bonding in 2-3 years, backside PDN in 3-4 years, with die-to-wafer bonding being a more future-oriented technology.

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    Takeru Hanaya's questions to ADVANTEST (ATEYY) leadership

    Takeru Hanaya's questions to ADVANTEST (ATEYY) leadership • Q1 2025

    Question

    Asked for a deeper explanation of the significant gross margin improvement in the new guidance. Questioned if the improvement was driven more by a change in the product mix *within* the SoC segment (i.e., a higher proportion of high-margin HPC/AI testers) rather than the overall SoC vs. memory mix.

    Answer

    The company confirmed the analyst's suggestion was correct. A major driver for the margin improvement is the favorable mix within the SoC business, as HPC-related test systems have richer configurations and higher average selling prices. Additionally, they have successfully executed on margin improvement initiatives for the memory business and benefited from a favorable mix within memory products as well.

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    Takeru Hanaya's questions to ADVANTEST (ATEYY) leadership • Q1 2024

    Question

    Takeru Hanaya from SMBC Nikko Securities inquired about the significant improvement in the gross margin guidance, from 48% to 52%. He suggested that the improvement might be driven more by a favorable mix shift within the SoC segment (HPC/AI vs. automotive) rather than just the overall SoC vs. memory mix.

    Answer

    Executive Douglas Lefever agreed that the favorable SoC mix was a key factor but also highlighted successful margin expansion initiatives in the memory business, including value-added features and economies of scale. An executive added that HPC-related business requires richer, higher-ASP test systems, which carry better margins, confirming the analyst's hypothesis about the mix within the SoC segment.

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