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    Taiwan Semiconductor Manufacturing Co Ltd (TSM)

    Q2 2024 Summary

    Published Feb 18, 2025, 5:22 PM UTC
    Initial Price$137.29April 1, 2024
    Final Price$172.33July 1, 2024
    Price Change$35.04
    % Change+25.52%

    What went well

    • TSMC is experiencing strong demand for its advanced process technologies, such as 3-nanometer and upcoming 2-nanometer nodes, with customers actively engaging in migration plans. This is expected to lead to higher revenue contributions and faster margin improvements compared to previous nodes.
    • The capacity constraints for leading-edge nodes are very tight, and TSMC is working diligently to increase capacity to support customers through 2026, which indicates a favorable pricing environment and the potential to sell more value to customers, enhancing profitability.
    • TSMC's investments in advanced packaging technologies, including fan-out panel-level packaging and super power rail (SPR), are expected to deliver significant benefits like power efficiency improvements, driving strong customer adoption and positioning TSMC favorably in emerging technology trends such as AI.

    What went wrong

    • TSMC faces capacity constraints in expanding leading-edge node production, with the CEO stating that capacity is "very, very tight" up to 2026, which may limit their ability to meet increasing customer demand and constrain revenue growth.
    • Pricing pressure from cost-sensitive smartphone customers could impact TSMC's margins. The company acknowledges that while HPC customers are "doing very, very well," smartphone customers are "more sensitive to the cost," suggesting potential challenges in maintaining pricing and profitability in that segment.
    • Delays in advanced packaging technologies like fan-out panel-level packaging could affect TSMC's competitiveness. TSMC expects that a mature solution for larger die sizes will take "at least 3 years," potentially putting them at a disadvantage if competitors offer such technologies sooner.

    Q&A Summary

    1. AI Capacity and CoWoS Expansion
      Q: When will AI capacity and CoWoS supply meet demand?
      A: Demand for AI accelerators and CoWoS advanced packaging is extremely high, and supply remains very tight. TSMC is working hard to meet customer demand but expects supply-demand balance may not be reached until 2025 or 2026. This year, CoWoS capacity has more than doubled, and TSMC plans to double it again next year, possibly more.

    2. Gross Margin Outlook
      Q: Will gross margins return to high 50s or 60%?
      A: TSMC aims for gross margins of 53% and higher, achievable through selling value, cost management, and efficiency improvements. While challenges like overseas fab dilution of 2–3 percentage points exist, higher utilization could boost margins, but the company maintains its target for now.

    3. Pricing Strategy and Value Selling
      Q: How is progress on selling value and pricing?
      A: Pricing is strategic, and TSMC continues to successfully sell its value to customers. All customers seek leading-edge capacity, and TSMC supports them in pricing and capacity, without changing its gross margin target but emphasizing the "and higher" in 53% and higher.

    4. Advanced Packaging Margins and Capacity
      Q: Are advanced packaging margins improving?
      A: Advanced packaging gross margins, previously below corporate average, are now approaching it due to economies of scale and cost reductions. TSMC is working with OSAT partners to increase CoWoS capacity, but supply is still insufficient to meet demand.

    5. N2 and A16 Capacity Plans
      Q: Can you support demand for N2 and A16 nodes?
      A: Customers are aggressively moving to N2, N2P, and A16 for power efficiency gains. TSMC is working hard to build capacity but acknowledges that supply is very tight. Efforts are ongoing to increase capacity over the next two years.

    6. Managing Demand Volatility
      Q: How are you managing demand volatility amid AI growth?
      A: TSMC employs a disciplined capacity planning process, learning from past experiences. The company believes AI demand is more real and sustainable, as AI becomes a useful tool across industries, and works closely with customers to ensure realistic forecasts.

    7. Geopolitical Risks and Mitigation
      Q: How are you mitigating geopolitical risks?
      A: TSMC continues its original overseas expansion plans with no changes, including fabs in Arizona, Kumamoto, and potential future sites in Europe. The company is not considering joint ventures or ownership sharing with governments.

    8. Smartphone and PC Silicon Content
      Q: Will AI increase silicon content in smartphones and PCs?
      A: AI functionality is increasing die sizes by 5–10%, though unit growth is not yet evident. TSMC expects AI integration to stimulate demand and potentially shorten replacement cycles, leading to unit growth in the next two years.

    9. N5 to N3 Conversion Plans
      Q: Will you convert more N5 capacity to N3?
      A: TSMC is considering further conversion from N5 to N3 due to strong N3 demand. High tool commonality of over 90% between the nodes allows flexibility, though N5 and N3 are not considered one big family.

    10. Impact of N3E on Gross Margins
      Q: Does N3E improve N3 gross margins?
      A: While N3E has different characteristics, TSMC doesn't break down margins by node. Overall, N3 dilution is improving, and the company expects continued enhancement of margins.

    11. Edge AI and Advanced Packaging
      Q: Are edge AI clients adopting advanced packaging?
      A: Customers moving to 2nm or A16 nodes are adopting chiplet approaches that require advanced packaging. HPC customers are transitioning faster than smartphone customers, who are now beginning to catch up, particularly with InFO technology.

    12. Bottlenecks in A16 Capacity Expansion
      Q: What are the bottlenecks in expanding A16 capacity?
      A: Expanding capacity requires land, electricity, and talented people—all of which are needed to support growth for advanced nodes like A16.

    13. Total System Power Savings with SPR
      Q: Can SPR save 20% of system power?
      A: A 20% power saving at the chip level doesn't directly translate to system-level savings, but it is significant. Since CPUs and accelerators are major power consumers, their efficiency gains contribute meaningfully to overall system power reduction.

    14. Fan-Out Panel-Level Packaging Plans
      Q: Any plans for fan-out panel-level packaging?
      A: TSMC is exploring panel-level fan-out packaging, but maturity isn't sufficient yet. It's expected to be introduced in at least three years, and TSMC is working on it.

    15. Tech Companies Accelerating Launch Cadence
      Q: How does accelerated product cadence affect TSMC?
      A: TSMC welcomes this trend and has been prepared, having discussed plans with customers well in advance. The company is ready to support customers' accelerated launch schedules.

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